The invention relates to an integrated semiconductor memory of the DRAM type, including word lines, bit line pairs, memory cells disposed in matrix form, and one evaluator circuit per bit line pair, each of the bit line pairs being divided into one bit line and one reference bit line during operation. The invention also relates to a method for testing an integrated semiconductor memory of the DRAM type, in which data stored in memory cells are read out of the memory cells and in which bit line pairs are precharged before the readout to a precharge level.
Integrated semiconductor memories of the generic type described above are known, for example, from the following publications:
IEEE Journal of Solid-State Circuits, Vol. SC-20, No. 5, Oct. 1985, pp. 903-908, "A 1-Mbit CMOS DRAM with Fast Page Mode and Static Column Mode". The publication discloses a generic integrated semiconductor memory with so-called "complementary capacitor coupled dummy cells". Possible dummy cells in this case include traditional dummy cells, in other words those constructed as one-transistor memory cells;
IEEE Journal of Solid-State Circuits, Vol. SC-22, No. 5, Oct. 1987, pp. 651-656, "A 65-ns 4-Mbit CMOS DRAM with a Twisted Driveline Sense Amplifier"; and
1984 IEEE International Solid-State Circuits Conference, ISSCC 84, Feb. 24, 1984, pages 278, 279 and 354, entitled "A Sub 100ns 256K DRAM in CMOS III Technology". Both publications show generic integrated semiconductor memories with dummy cells.
When testing integrated semiconductor memories of the DRAM type, it would often be desirable to be able to detect not only the properties that are usually detectable, such as current consumption, functional capacity, and sensitivity to certain test patterns, but also properties that determine the operating range of various circuit parts of a semiconductor memory (such as cell capacitance, symmetry of memory cells at bit lines and reference bit lines, and symmetry of evaluator circuits). Heretofore, this could only be done, for instance, by applying supply potentials having values outside the range defined by the specification, for components mounted in their final form. The same is true for the level of input signals. On the wafer level, it has so far additionally been possible to supply auxiliary signals and/or auxiliary potentials for analysis and test purposes, for instance with the aid of so-called supplementary pads that are accessible only before a semiconductor memory is provided with a housing.
A further option for analysis on the wafer level is purposeful irradiation of the semiconductor memory with alpha particles. However, all of these options exert a rather global influence on the semiconductor memory. In other words, regions outside the memory cell field are usually undesirably affected as well.